Traditionally, techniques such as physical vapor deposition (PVD) of gold tin solder (e.g., sputtering or evaporation), plating, or attaching preforms were used to seal wafer level packaged electronic devices using solder. If one of the various PVD methods are used, the process may include extra processing steps (e.g., lithography for wet etch or lift-off) and the waste of expensive materials (e.g., the bulk of the deposited metals may be removed). The PVD methods also do not, as a practical matter, allow for very tall bond lines (typically less than 3 micrometers high). If plating is used to bond two components, it may not be possible to have a high vacuum inside the sealed device because plated metals are porous and have high outgassing characteristics. If preforms are used, they may be manually aligned and attached, resulting in extensive touch labor which can be expensive and inaccurate. Preforms may also be limited in size. Additionally, commercial wafer bonders for wafer level packaging may employ spacers in the order of 100 um-200 um to maintain a gap between the two substrates before actual bonding. This small gap may inhibit creating a high vacuum inside the sealed device due to a low vacuum conductance.
One common problem with many of the above methods is the high risk of blow-outs. Blow-outs may occur when the small change in cavity volume during the bonding process causes a large change in cavity pressure differential. This pressure differential may then attempt to escape by blowing out the melted solder. The blow-out could damage the seal and potentially short the electronic device being sealed.